1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device containing a sense amplifier for amplifying the potential difference between bit lines with fewer faulty operations.
2. Description of the Related Art
With advances in integrated-circuit technology, semiconductor memory devices, especially dynamic random access memories (hereinafter, referred to as DRAMs) have been used widely in the field of electronics. A DRAM memory cell is basically composed of one transistor and one capacitor. DRAMs are suitable for high integration because of a smaller number of elements used and are less expensive in bit unit price, with the result that they are used in large numbers for computers, communication equipment, and image processing equipment. Information is memorized in the form of the charge stored in a capacitor. To retain the information, the operation of reading and writing at regular intervals of time, known as refresh, is required.
FIG. 1 is a block diagram of a DRAM, showing the basis configuration. Referring to the figure, the flow of signal will be explained. In synchronization with the row address strobe signal (BRAS) and the column address signal (BCAS), the row address input and the column address input enter the row address buffer 120 and the column address buffer 121 and are latched there, respectively, in a time division manner. A row decoder 123 selects and drives a word line (not shown) and thereby accesses the desired row of memory cells in a memory cell array 100.
The information in the memory cells in the accessed row is transferred to a bit line (not shown) and amplified at a sense amplifier 105. At the same time, the information is rewritten into the memory cells.
A column decoder 124 selects and drives a column selection gate 125 according to the column address input and thereby selects the output of the sense amplifier 105 corresponding to the desired column. The selected information is read onto a data line (not shown) and transferred to an I/O buffer 102 via a data bus 101. The I/O buffer 102 is connected to an external I/O section (not shown).
The series of operations is controlled by an internal synchronizing signal and executed in a predetermined sequence with predetermined timing to prevent the memory cell information from being destroyed.
FIG. 2 is a circuit diagram of a conventional DRAM sense amplifier and an equalizer circuit which is omitted in FIG. 1. The same parts as those in FIG. 1 are indicated by the same reference symbols.
As shown in FIG. 2, there are provided a bit line BL connected to a memory cell (not shown) in the memory cell array 100, and a bit line BBL connected to another memory cell (not shown) and paired with the bit line BL. The bit lines BL, BBL connect the memory cells to the DQ bus 101. The column selection gate shown in FIG. 1 is not shown in FIG. 2. The DQ bus 101 is connected to the I/O buffer 102. The I/O buffer 102 exchanges data from outside the device to the DQ bus 101 and from the DQ bus 101 to outside the device.
Between the bit lines BL and BBL, there is provided a bit-line equalizer 103 for equalizing the potential difference between the potential of the bit line BL and that of the bit line BBL. The equalizer 103 is turned on and off by the equalize signal BEQ from a row controller 104.
Between the bit lines BL and BBL, there is also provided a sense amplifier 105 for amplifying the potential difference between the potential of the bit line BL and that of the bit line BBL. The sense amplifier 105 is driven by a sense amplifier driver 106 activated by an activate signal SEN from the row controller 104. The sense amplifier 105 contains a PMOS FET (P channel type MOS field effect transistor) sense amplifier section and an NMOS FET (N channel type MOS field effect transistor) sense amplifier section 108. A driving signal line SAP is connected to the PMOS FET sense amplifier section 107 and a driving signal line BSAN is connected to the NMOS FET sense amplifier section 108.
FIG. 3 is a circuit diagram of the sense amplifier driver 106 shown in FIG. 2. As shown in FIG. 3, the sense amplifier driver 106 contains a PMOS FET 110 that supplies a VCC level signal as a driving signal to a driving signal line SAP, an NMOS FET 113 that supplies a VSS level potential (e.g., the ground potential) as a driving signal to a driving signal line BSAN, an NMOS 111 that supplies a VBL level (about VCC/2 level) potential as a precharge potential to a driving signal line SAP, and an NMOS FET 112 that supplies about a VBL level potential as a precharge potential to a driving signal line BSAN.
In the conventional sense amplifier driver 106, the driving signal line pair SAP, BSAN is precharged by using the equalize signal BEQ that is used to equalize the sense amplifier.
Since the activate signal SEN is output later than the equalize signal BEQ, however, the conventional sense amplifier driver 106 permits the occurrence of a period of time during which the potentials of the driving signals SAP, BSAN are unstable (floating) as shown in the operating waveform diagram of FIG. 4. When noise is introduced to the driving signal line SAP or BSAN during a period when the potential is unstable, the potential of the driving signal line can change to an H (high) level or an L (low) level. When the potential of the driving signal line goes to the H level or the L level, this will allow power to be supplied to the sense amplifier 105, resulting in a chance of a faulty operation taking place. As described above, the conventional sense amplifier driver has contained a factor that permits faulty operations.